1. Field of the Invention
This invention relates to an epitaxial silicon wafer and a production method thereof.
2. Description of the Related Art
Silicon wafers used in semiconductor devices are generally called bulk wafers or epitaxial wafers. A bulk wafer is a mirror-finished wafer formed by slicing an ingot-shaped silicon single crystal grown using, for example, a Czochralski method (CZ method) into a disc-shaped wafer and then polishing a surface thereof. On the other hand, an epitaxial wafer is formed using a mirror-finished wafer as a wafer for epitaxial growth and further growing a silicon single crystal silicon on the wafer for epitaxial growth using an epitaxial technique.
In principle, damage or strain due to polishing, as occurs in the mirror-finished wafer, is not existent for an epitaxial wafer. Therefore, it is known that epitaxial wafers show improved properties compared to mirror-finished wafers in the field of semiconductor devices requiring a higher quality, but epitaxial wafers are not widely put into practice because of high production cost.
However, a large-size wafer having a diameter of 450 mm has now been developed to increase cost per epitaxial wafer and also high-quality epitaxial wafers are increasingly associated with ultra-miniaturization of devices.
As previously mentioned, the epitaxial wafer is formed by growing an epitaxial layer on the wafer for epitaxial growth. In this case, the wafer for epitaxial growth has a low resistance and the epitaxial layer has a high resistance. A mismatch of lattice constant is caused therebetween, and warping may be caused to mitigate strain between atomic layers. Such a warping leads to chucking and transfer issues and increases with an increase in the diameter of the wafer.
Patent Document 1 proposes a method of producing an epitaxial silicon wafer in which an epitaxial layer is formed on a surface of a silicon wafer for epitaxial growth having a concaved surface by identifying an unevenness of a warped form in the silicon wafer for epitaxial growth and then estimating warping produced when the epitaxial layer is formed on the wafer surface.
[Patent Document 1] JP-A-H06-112120
In this production method, the warping produced in the epitaxial growth is offset by previously identifying the warping in the surface of the silicon wafer for epitaxial growth and rendering the direction of the warping into a direction opposite to a changing direction of warping produced in the epitaxial growth, whereby an absolute value of the warping in the epitaxial silicon wafer can be reduced. However, the warping in the surface of the silicon wafer for epitaxial growth is randomly formed in the slicing step and does not necessarily correspond to the change of the warping produced in the epitaxial growth.
Then, the inventors have proposed an epitaxial silicon wafer enabling reduction of warping amount by forming an epitaxial layer on a surface of a silicon wafer for epitaxial growth to which a bowl-shaped warping having a concaved central portion is given by subjecting a thin disc-shaped wafer to either grinding or polishing or both treatments in Patent Document 2.
[Patent Document 2] JP-A-2008-140856
This wafer is obtained by forming an epitaxial layer on a silicon wafer for epitaxial growth having a cross-sectional shape formed so as to satisfy the following expression (5), which is determined by the following expression (3) and (4) introduced by a conventional method, and can provide a flat epitaxial silicon wafer by offsetting the warping produced in the growth of epitaxial layer.
                              ɛ          1                =                              1            3                    ⁢                      (                                          t                si                2                                            t                epi                                      )                    ⁢                      (                          δ                              r                2                                      )                                              (        3        )                                          ɛ          2                =                                            Δ              ⁢                                                          ⁢                              a                                  si                  -                  B                                                                    a              si                                =                                                    -                2.69                            ×                              10                                  -                  23                                            ×                              [                B                ]                                      5.43                                              (        4        )                                δ        =                                                            -                2.69                            ×                              10                                  -                  23                                            ×                              [                B                ]                                      5.43                    ×          3          ×                      r            2                    ×                      (                                          t                epi                                            t                si                2                                      )                                              (        5        )            
In the expression (3), ε1 is strain in an epitaxial layer, tsi is a thickness of a silicon wafer for epitaxial growth, tepi is a thickness of an epitaxial layer, δ is the warping of an epitaxial silicon wafer and r is a radius of a wafer. In the expression (4), ε2 is strain based on a difference in lattice constant between a silicon wafer for epitaxial growth and an epitaxial layer, [B] is a boron concentration, Δαsi-B is a difference in lattice constant between of a silicon wafer for epitaxial growth having [B] and a non-doped epitaxial layer and αsi is a lattice constant of an epitaxial layer. Also, it is assumed that strain ε1 in the epitaxial layer is equal to strain ε2 based on a difference in lattice constant between a silicon wafer for epitaxial growth and an epitaxial layer.
In the method described in Patent Document 2, an epitaxial silicon wafer with reduced warping can be provided by offsetting the warping produced in the growth of epitaxial layer as compared with the conventional method in which an epitaxial layer is grown using a wafer for epitaxial growth having no rationalization of cross-sectional form (that is, having a flat form without warping), but it is not sufficient. Particularly, the warping is not sufficiently reduced in an epitaxial silicon wafer having a large diameter of not less than 450 mm, and further improvement is required.